The fabrication of semiconductor devices typically includes the depositing and patterning of insulating layers and conductive layers. In general, the fabrication of a device can start with the patterning of a semiconductor substrate into active area portions separated from one another by insulation. Subsequent alternating insulation and conductive layers are then formed over, and sometimes coupled to the substrate, to interconnect the various circuit elements within the device (such as transistors, capacitors, resistors and the like).
The patterning of an insulating or conductive layer can be accomplished using a lithography and etch step. The lithography step involves depositing an alterable material, referred to as a "resist" on the layer that is to be patterned. The resist is then "developed" or "printed" into a pattern by the application of some form of radiation. For example, "photoresists" can be patterned by the application of light. Other resists can be patterned by x-rays, electron beams or ion beams, to name just a few examples. The pattern within a resist is typically developed by situating a "mask" containing the desired pattern over the resist. The mask includes "transparent" portions that will allow radiation to pass through, and "blocking" portions that will block the radiation. When the radiation is applied, the areas of resist situated below the transparent mask portions will be developed while those below blocking portions will not be developed. The undeveloped portions of resist can then be removed with a solvent, leaving the desired pattern over the fabrication layer. In the case of photolithography, the developing of resist will depend on the intensity of the light applied to the resist.
The developed pattern of resist can then serve as an etch mask for the fabrication layer below. An etch can be applied, and those portions of the fabrication layer that are covered by the etch mask will be protected from the etch. The exposed portions of the fabrication layer will be removed. In this manner, structures or "features" are formed in the fabrication layer by the etch step. For example, in the event the fabrication layer is a conductive layer, the etch step can create conductive interconnects between various portions of a device. In the event the fabrication layer is an insulation layer, the etch step can create contact holes through the insulation layer to a conductive layer below.
In order to fabricate as small a semiconductor device as possible, and hence produce such devices in a more cost-effective manner, efforts are continually made to form features with as small a size as possible. The smallest manufacturable feature size is often referred to as a minimum feature size. The minimum feature size will determine how close structures can be situated relative to one another in the semiconductor device. In addition to impacting the resulting size of a semiconductor device, feature sizes can also affect the functionality of a semiconductor device. For example, in order to create accurate etch mask patterns from a layer of resist, sufficient radiation must be applied to the resist to print the pattern. However, as masks are made for devices having increasingly smaller features sizes, it becomes more and more difficult to control the resulting radiation intensity necessary to produce uniform feature sizes across a semiconductor device.
A drawback to prior art conventional photolithography approaches is set forth in FIG. 1. FIG. 1 includes a portion of a photolithography mask 100 ("photomask") that includes transparent portions 102 and blocking portions 104. Ideally, the two transparent portions 102 would create two distinct intensity patterns, and thus produce two adjacent features. Set forth below the photomask 100 is a first graph 106 illustrating the amplitude of the light waveforms that result from the photomask 100. Below the first graph 106 is a second graph 108 setting forth the resulting light intensity provided by the photomask 100 transparent portions 102. The intensity graph 108 shows that when smaller feature sizes are required, it is difficult to achieve two distinct intensity waveform, and thus two distinct features.
FIG. 2 illustrates one approach to producing smaller features sizes using the same light wavelength as that shown in FIG. 1. FIG. 2 includes a photomask 200 having transparent portions 202a and 202b, as well as blocking portions 204. However, unlike the photomask 100 of FIG. 1, the photomask 200 of FIG. 2 is a phase-shifted photomask. Thus, while the transparent portions (202a and 202b) allow light to pass through, transparent portion 202b introduces a phase shift in the light with respect to transparent portion 202a. The phase shift may be accomplished by making the transparent portion 202b from a different material, different combination of materials, or a different thickness than transparent portion 202a.
The resulting light amplitude response of the phase-shift mask 200 is set forth in a first graph 206. As shown, the light provided by transparent portion 202b is shifted in phase, by approximately 180.degree., from that provided by transparent potion 202a. The resulting light intensity is shown in a second graph 208. As shown in the second graph 208, the phase shift causes the resulting intensity between the two peaks to be less, due to interference effects. Consequently, a better intensity profile, and hence better resist etch mask can be created. In this manner, phase shifted masks can create smaller minimum feature sizes than conventional (non phase-shifted) lithography approaches. It is noted however, that adjacent features must be patterned by using light of opposing phases.
One particular type of semiconductor device in which minimum feature sizes can play an important role is the semiconductor memory device. Semiconductor memory devices typically ihclude an array of densely packed memory cells that are connected to one another by conductive lines. In most random access memory (RAM) and read-only-memory (ROM) configurations, the memory cells are arranged in rows and columns. Densely packed conductive lines are disposed over the memory cells and can include bit lines, extending in the column direction, and word lines extending in the row direction. In order to provide as dense a device as possible, it is advantageous to make the conductive lines with as small a feature size as possible.
Conventional bit line layouts (i.e., a series of parallel lines) can benefit from phase-shifted mask approaches by alternating the phase of the light used to pattern adjacent bit lines. For example, the light used to pattern even bit lines could be at one phase, while the phase of light used to pattern odd bit lines is shifted by 180.degree.. Unfortunately, for more complex bit lines, phase-shifted masks may not be applicable.
An example of a bit line arrangement that is not conducive to phase shifted masks is set forth in FIG. 3. The bit line arrangement of FIG. 3 is a "triple twist" bit line arrangement, and is designated by the general reference character 300. The arrangement 300 is shown to include first twisted bit line pairs (302a and 302c) and a second twisted bit line pair 302b. The bit line pairs (302a and 302b) are considered "twisted" in that the orientation of the bit lines within each pair switches with respect to one another. For example, the bit line pair 302a includes a first bit line 304a and a second bit line 304b. Toward the top of the figure, bit line 304a is to the left of bit line 304b. Toward the bottom of FIG. 3, bit line 304a is to the ,right of bit line 304b. In a similar fashion, bit line pair 302b includes a first bit line 304c that is disposed to the left of a second bit line 304d at the top of the figure. After a first twist, bit line 304c is to the right of bit line 304d. After a second twist, bit line 304c is once again to the left of bit line 304d. Twisted bit line arrangements are advantageous as they distribute capacitively coupled signals from both sides of a bit line pair to both bit lines of the bit line pair. This cross coupling results in more common mode noise. Common mode noise is rejected by most data detection amplifiers (sense amplifiers) allowing for more effective data signal detection, and hence smaller memory cells and/or faster operating speeds.
In the bit line arrangement of FIG. 3, the bit line twisting is accomplished by twist structures 306. Each bit line pair (302a-302c) can be considered to include an integral bit line and a segmented bit line. The integral bit lines are integral structures that extend in the column direction and switch position in the bit line pairs inside the twist structures 306. In FIG. 3, bit lines 304b, 304d, and 304f are integral bit lines. The segmented bit lines include individual segments that are in alternating positions within the bit line pair, and are connected to one another by a cross-over element 308 within each twist structure 306. In FIG. 3, bit lines 304a, 304c and 304e are segmented bit lines. The cross-over elements 308 are formed from a different conductive layer than the integral bit line structures and bit line segments, and are therefore represented in FIG. 3 by dashed lines.
The bit line arrangement 300 of FIG. 3 is not conducive to phase-shifted masks because it is not possible to make adjacent structures using opposite phase light sources. This is best understood with reference FIG. 4. FIG. 4 sets forth a portion of the triple twist bit line arrangement of FIG. 3. The view of FIG. 4 represents the first conductive layer (the cross-over structures are omitted). As noted previously, in order for the interference effects of phase-shifted masks to be effective, adjacent features must be formed by the application of light having opposite phases. Toward the bottom of the figure, phase symbols are set forth to represent the phase used to form the structures. The symbol "0" represents one phase while the symbol ".pi." represents an opposite phase (a 180.degree. phase shift, for example). While opposing phases can be maintained by the various features at the bottom of the figure, the particular twisting arrangement makes it impossible to maintain opposite phase toward the top of the figure. As just one example, integral bit line 402 cannot be of opposite phase to bit line segment 404 and adjacent bit line 406, and also be of opposite phase to the other adjacent bit line 408. Thus, the triple twist bit line arrangement of FIGS. 3 and 4 cannot be formed using phase-shifted mask techniques, and so cannot benefit from the small feature sizes attainable by such techniques.
A twisted bit line arrangement that can take advantage of phase-shifted mask approaches is set forth in FIG. 5. The twisted bit line arrangement is designated by the general reference character 500, and does not include integral bit lines that switch position within the bit line pair, and thus is conducive to phase-shifted mask approaches. Referring to FIG. 5, the bit line arrangement 500 is shown to include first bit line pairs 502a, 502c and 502e that alternate with second bit line pairs 502b and 502d. The first bit pairs (502a, 502c and 502e) each include integral bit line portions that extend in the column direction. For example, the integral bit line portions of bit line pair 502a are shown as items 504a and 504b. The second bit line pairs (502b and 502d) include a pair of upper bit line segments and lower bit line segments that are connected to one another in a "twisted" fashion by twist structures (506a and 506b). For example, bit line pair 502b includes upper bit line segments 508a and 508b and lower bit line segments 510a and 510b. Twist structure 506a includes a first cross-over element 512a that connects upper bit line segment 508a to lower bit line segment 510b, and a second cross-over element 512b that connects upper bit line segment 508b to lower bit line segment 510a. Twist structure 506a is shown to be generally aligned with twist structure 506b in the horizontal direction of FIG. 5.
The cross-over elements (512a and 512b) are formed from a different layer than that of the bit line segments, and so are shown as a dashed line. Thus, the bit line and bit line segments shown by a solid line in FIG. 5 can be considered to be formed from a first conductive layer, and the cross-over elements (512a and 512b) can be considered to be formed from a second conductive layer. The light phases used to form the various bit line and bit line segments of the first conductive layer are shown in FIG. 5 by the symbols "0" and ".pi.." As shown in the figure, all adjacent features are of an opposite phase. Thus, the prior art bit line arrangement of FIG. 5 can be formed with a phase-shifted mask.
FIG. 5 further includes a supplementary conductive line shown as item 514. Supplementary conductive line 514 is formed from the same layer as the cross-over elements (512a and 512b), and so is also shown as a dashed line. The use of supplementary conductive lines can be particularly advantageous in dense memory device arrangements for carrying signals such as timing signals and/or column select signals.
A drawback to the twisted bit line arrangement if FIG. 5 arises out of the structures formed from the second conductive layer. The cross-over elements (512a and 512b) and supplementary conductive line 514 are shown to be separated from one another by the same spacing ("pitch") as the structures of the first conductive layer. Thus, the arrangement of FIG. 5 relies on the fact that the minimum spacing achievable by the first conductive layer is also achievable by the second conductive layer. Unfortunately, this is not always possible. The material of the second conductive layer or the lithographic steps used to pattern the second conductive layer, may force the minimum spacing requirements of the second conductive layer to be greater than that of the first conductive layer. In such a case, it may not be possible to create a bit line arrangement that retains enough room for supplementary conductive line, such as line 514 shown in FIG. 5.
In light of the above bit line arrangements and their accompanying drawbacks, it would be desirable to provide a twisted bit line arrangement that includes a compact bit line arrangement formed using phase-shifted lithography steps from a first conductive layer, that also allows for a larger pitch second conductive layer that can accommodate supplemental conductive lines.